VESIT, Chembur gets a grant of Rs 82.59 lakh from MeitY for an innovative project proposal for VLSI chip design
Mumbai 24th May 2023: V.E.S Institute of Technology (VESIT) has announced that the Ministry of Electronics and Information Technology (MeitY), under their esteemed “Chips to Startup (C2S)” program, has awarded a grant of Rs 82.59 lakh for a ground-breaking project proposal.
The project, an extension of the Ph.D. work undertaken by Dr. Nilima Warke, Associate Professor, Automation & Robotics Department, and Dr. Jayamala Adsul, Assistant Professor, Electronics dept, VESIT under the mentorship of Dr. P. P. Vaidya, Hon. Dean R&D, will be implemented in collaboration with Shri. Amit Rambhia, Chairman and Managing Director of Panache Digilife Ltd, is an esteemed graduate of VESIT.
The project proposal stood out among numerous submissions due to its innovative nature and potential for significant contributions to the field of electronics. With this grant, VESIT will be able to further the research and development efforts of Dr. Warke and Dr. Adsul, advancing their pioneering work and opening new avenues for technological advancements.
In addition to the grant money, VESIT has been granted remote access to development tools worth more than Rs. 1 crore, providing the necessary resources to facilitate the project’s successful implementation. This collaboration and support from MeitY will enable VESIT to continue its mission of fostering research and innovation within its academic community.
Principal Dr.(Mrs.) J.M. Nair, VES Institute of Technology expressed her elation, stating: “We are very delighted that the Ministry of Electronics and Information Technology (MeitY) has awarded VESIT a generous grant under the ‘Chips to Startup’ program. It is for the first time the institute is receiving a research grant for VLSI chip design. The research grants received earlier were in the IT and Nuclear domain. Last year, another project developed in the VESIT R&D lab received a Start-up grant of Rs. 25 lakhs from MeitY. The C2S grant will also give motivation to other researchers working on hardware research projects. We hope that this will also facilitate the chip implementation of other projects developed in the state of art R&D lab in the institute.
This grant also envisages generating an industry-ready skilled workforce in the domain of VLSI. VESIT has already applied to AICTE and Mumbai University for starting a PG course in “VLSI and Embedded Systems” from the academic year 2023-24. This further will help to inculcate the culture of System-on-Chip (SoC)/System Level Design and act as a catalyst for the growth of start-ups in fabless design. We extend our heartfelt gratitude to the Ministry for recognizing the potential of this project and for their valuable support.”
Principal Nair remarked: “We are immensely thankful to the VES management for their unwavering support in creating an environment conducive to research and innovation. Additionally, we extend our gratitude to Shri. B. L. Boolani, Managing Trustee, VESIT for his special interest in promoting and fostering a culture of research and innovation within the institute. This academia-industry collaboration exemplifies the institute’s commitment to driving technological advancements and nurturing talent.”
The self-financed institute known for its ” No capitation fee for admission ” is excited about this opportunity to contribute to the development of the technology landscape and looks forward to the successful execution of the project, which holds tremendous potential for societal and economic impact.